1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory such as EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory (collectively electrically erasable EEPROM), etc. and a method of operating the same and, more particularly, a nonvolatile semiconductor memory capable of assuring stable write verification and erase verification when a decision current or a decision voltage is varied due to a power supply noise and other causes, and a method of operating the same.
2. Description of the Prior Art
In recent years, multi-functioning and size reduction of the electronic device are accelerated, and thus miniaturization of the semiconductor integrated circuit is required much more correspondingly. In the nonvolatile semiconductor memory such as EEPROM, the flash memory, etc., not only the miniaturization of the memory cell but also the stable detection of smaller change in the threshold voltage is required.
In the meanwhile, the memory whose substantial cell area can be reduced without shrinkage in the dimension of the memory cell and which can respond to the multi-level operation has also been developed. In the normal semiconductor memory, only two states of “0” or “1” can be stored in one memory cell. While, in the multi-level memory, three states or more can be stored in one memory cell. In this case, in the multi-level memory, the threshold voltage must be strictly controlled in response to the stored data. In future, in order to respond to the higher functioning and size reduction of the electronic device, the multi-level memory will be positively employed.
As the nonvolatile semiconductor memory in the prior art, the floating gate memory having the dual gate structure, in which two gate electrodes of the floating gate and the control gate are formed to put the thin insulating film therebetween, is used commonly. The floating gate memory is set forth in Patent Application Publication (KOKAI) 2000-174235, for example.
However, in recent years, complicated manufacturing processes required for the dual gate structure becomes conspicuous as the obstacle to the miniaturization. For this reason, the single gate nonvolatile semiconductor memory having one gate electrode is watched with interest. In the single gate nonvolatile semiconductor memory, the material that can store the charge therein is employed as the gate insulating film that is formed between the semiconductor substrate and the gate electrode, and then data are stored by utilizing such a phenomenon that the threshold voltage is changed according to an amount of charge stored in the gate insulating film.
As one of such single gate nonvolatile semiconductor memories, there is the SONOS (Silicon Oxide Nitride Oxide Silicon) memory. This SONOS memory is set forth in Patent Application Publication (KOKAI) 2001-325793, for example.
In the SONOS memory, the insulating film having the laminated structure in which the silicon nitride (SiN) film is put between the silicon oxide (SiO2) films vertically, for example, is employed as the gate insulating film. The storing and erasing of data are executed by loading/unloading the charge into/from the silicon nitride film.
In the SONOS memory, since an amount of trapped charge is smaller than the floating gate memory, an amount of shift of the threshold voltage is small. Also, in the SONOS memory, since a writing efficiency is low, a writing rate become slower than the floating gate memory. Therefore, in the single gate nonvolatile semiconductor memory such as the SONOS memory, it is important to detect a minute change in the threshold voltage during the writing and the erasing.
In this manner, in view of the tendency of the nonvolatile semiconductor memory in recent years, it is important to detect a minute change in the threshold voltage. However, such a problem is caused that, if an amount of change in the threshold voltage is small, the pass or the fail cannot be decided precisely in the verifying operation to check whether or not the writing and the erasing have been sufficiently executed.
More particularly, in the semiconductor memory, a current serving as a criterion or a current supplied from the memory cell is varied on a time-dependent basis by the influence of the external noise such as the power supply noise and others. Thus, in some cases a voltage that corresponds to a fluctuation level of the current caused by the influence of these noises become equal to an amount of change in the threshold voltage. As a result, in some cases the memory cell that has been decided once as the pass is decided as the fail in the next verification, and thus the writing or erasing operation (loop) must be executed once again. In this case, if there is the memory cell that has been decided as the fail in the second verifying operation, the writing or erasing operation (loop) must be further executed. In this manner, in the nonvolatile semiconductor memory in the prior art, the pass/fail decision becomes unreliable by the influence of the power supply noise and others, and thus it is possible that the verifying operation should be executed many times.
FIG. 1 is a view showing a concept of verification in the prior art. It is assumed that a reference current I is varied only by ±ΔI. If a current Id of the memory cell is in excess of I+ΔI, the memory cell is decided as the fail irrespective of the influence of the noise, and thus the writing is needed once again. If the current Id of the memory cell is below I−ΔI, the memory cell is decided as the pass irrespective of the influence of the noise, and thus the second writing is not needed. However, if the current Id of the memory cell is in the range of I−Δ I<Id<I+ΔI, the pass/fail decision becomes unreliable because of the influence of the noise. As a result, sometimes the cell that has been decided as the pass in the first verification is decided as the fail in the next verification.
In the actual memory, as shown in a conceptual view of FIG. 2, there are three decision levels, i.e., the write decision level, the stored information decision level at the normal operation, and the erase decision level. The dead band in which the decision becomes unstable (the band indicated by a broken line in FIG. 2) exists at each decision level.
FIG. 3 is a flowchart showing the write verifying operation in the nonvolatile semiconductor memory in the prior art.
First, in step S11, a fail count is initialized (fail count=0). Then, in step S12, a start address is set in an address counter. In step S13, data is read from the memory cell whose address is the start address.
Then, the process goes to step S14 to decide whether or not a memory cell is the memory cell of which the data writing is required. If the memory cell is the memory cell of which the data writing is required, it is decided by comparing read data with a criterion whether or not the read data is fail. If the memory cell is the memory cell of which the data writing is required and the read data is fail (Yes), the process goes to step S15. In contrast, if the memory cell is the memory cell of which the data writing is not required or if the read data is pass (No), the process goes to step S17.
In step S15, a write pulse is applied the memory cell having the address. Then, the process goes to step S16 in which the number of fail count is incremented by 1. Then, the process goes to step S17.
In step S17, it is decided whether or not the address that is set in the address counter is the end address. If the address is not the end address, the process goes to step S18 to set the next address in the address counter. Then, the process goes back to step S13, the data is read from the memory cell that has the set address.
In this manner, the data is read sequentially from the memory cell having the start address through the memory cell having the end address to decide whether or not the memory cell is the memory cell of which the data writing is required and then decide whether or not the read data is fail if the memory cell is the memory cell of which the data writing is required. Then, an amount of charge stored in the memory cell that was decided as the fail is changed by applying a write pulse to the memory cell.
Then, the process goes from step S17 to step S19 to decide whether or not the number of fail count is 0. If the number of fail count is not 0, the process goes back to step S11 and then the above processes are repeated. If it is decided in step S19 that the number of fail count is 0, the verification is ended.
FIG. 4 is a flowchart showing the erase verifying operation in the nonvolatile semiconductor memory in the prior art.
First, in step S21, the fail count is initialized (fail count=0). Then, in step S22, the start address is set in the address counter. In step S23, the data is read from the memory cell whose address is the start address.
Then, the process goes to step S24 wherein the read data is compared with the criterion to decide whether or not the read data is fail. If the read data is fail (Yes), the process goes to step S25. If the read data is pass (No), the process goes to step S26.
In step S25, the number of fail count is incremented by 1. Then, the process goes to step S26.
In step S26, it is decided whether or not the address that is set in the address counter is the end address. If the set address is not the end address, the process goes to step S27 wherein the next address is set in the address counter. Then, the process goes back to step S23 wherein the data is read from the memory cell that has the set address.
In this manner, the data is read sequentially from the memory cell having the start address through the memory cell having the end address to decide whether or not the read data is fail. The number of fail count is incremented every time when the fail is sensed.
Then, the process goes from step S26 to step S28 to decide whether or not the number of fail count is 0. If the number of fail count is not 0, the process goes to step S29 in which an erase pulse is applied collectively to all the memory cells that have the start address to the end address. Then, the process goes back to step S21, and the above processes are repeated. In addition, in the erase verification, as shown by a broken-line arrow in FIG. 4, there is also the case that the process goes directly to step S29 if the fail is detected in step S24.
As shown in FIG. 3 and FIG. 4, in the nonvolatile semiconductor memory in the prior art, if the fail occurs at the time of verification, the application of the write pulse or the erase pulse is repeated until the fail can be eliminated. As described above, it is impossible to say that, since sometimes the memory cell that was decided as the pass due to the influence of the noise, etc. is decided as the fail in the next verification, the nonvolatile semiconductor memory in the prior art has the sufficient reliability. Also, the process loop (processes in step S11 to step S19 or step S21 to step S29) is repeated many times until the fail can be eliminated. Thus, it takes a lot of time until the verification is completed.